State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing

Authors : Hemalatha K N, Sangeetha B G

Pages : 249-261

Doi:10.35378/gujs.937858

View : 18 | Download : 7

Publication Date : 2023-03-01

Article Type : Review Paper

Abstract :Multiplication is the key crucial operation in realizing digital signal processing insert ignore into journalissuearticles values(DSP); functions. It is accomplished by using diverse multiplier architectures. Multiplication operation is furthermost basic and normally used action in the central processing unit insert ignore into journalissuearticles values(CPU);. The multiplication operation is the most fundamental and commonly performed activity in the central processing unit insert ignore into journalissuearticles values(CPU);. An efficient multiplier design should have a high speed, small area, and a low power consumption. Compact, efficient multipliers with minimal power dissipation are needed. The proposed paper provides a thorough inspection of multipliers such as the Array multiplier, Booth multiplier, column bypass multiplier, Baugh-Wooley multiplier, and Vedic multiplier based on their operational activities and working, as well as their benefits and limits. A comparison of these multipliers\` performance parameters such as speed, area, power consumption, quantum cost, garbage generation and circuit complexity.
Keywords : Reversible logic, Array multiplier, Booth multiplier, Vedic multiplier, Quantum cost