An Energy-efficient Parallel ASIC Implementation of Advanced Encryption Standard (AES) Algorithm Robust against Side-channel Attacks

Encryption becomes more crucial than ever in an increasingly interconnected world. Advanced Encryption Standard (AES) is still considered secure after more than 20 years thanks to its mathematical properties. However, side-channel attacks (SCA) threaten improper AES implementations. In this paper, different AES implementations are introduced, and their resistances against power SCA, namely Correlation Power Analysis (CPA) attack, are shown. For energy efficiency, the increase in power consumption due to the extras added for countering SCA was minimized by register-level organizations and process-related optimizations. Different AES implementations were constructed and processed through Cadence ASIC flow (TSMC 65 nm LP technology). SCA resistance was evaluated using the ChipWhisperer platform operating on realistic power consumption values obtained after RTL-to-GDSII flow. The results demonstrate that pipelining and unrolling the AES rounds increase the SCA resistance at the expense of a minimal reduction in energy efficiency. The proposed implementations are suitable for use with different side-channel attack countermeasures.