Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

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Sakarya Üniversitesi Fen Bilimleri Enstitüsü Dergisi
Volume:25 Issue:6
Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Authors : Dursun BARAN

Pages : 1386-1393

Doi:10.16984/saufenbilder.877453

View : 28 | Download : 15

Publication Date : 2021-12-31

Article Type : Research Paper

Abstract :Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.
Keywords : Parallel FFT Core, Real Time Spectrum Analysis, Energy Efficient Design, FPGA

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