Low power 3rd order feedforward sigma delta ADC design

Home Page
About
Submit A Journal
Submit A Conference
Submit Paper/Book
- Submit a Preprint
- Submit a Book
Contact

Turkish Journal of Electrical Engineering and Computer Science
Volume:25 Issue:1
Low power 3rd order feedforward sigma delta ADC design

Low power 3rd order feedforward sigma delta ADC design

Authors : FEYYAZ MELİH AKÇAKAYA, GÜNHAN DÜNDAR

Pages : 155-162

View : 10 | Download : 13

Publication Date : 0000-00-00

Article Type : Research Paper

Abstract :In this work, a 3-bit feedforward 3rd order sigma delta analog-to-digital converter insert ignore into journalissuearticles values(ADC); is presented. In this proposed architecture, feedforward paths and multibit design help the integrator output swings to become smaller, which renders the exploitation of a telescopic cascode opamp in the integrators possible. Moreover, a double sampling method is used to relax the opamp specifications. The proposed sigma delta ADC consumes 28.2 $\mu $W and has 81.3 dB SNDR according to postlayout simulations.
Keywords : Sigma delta, analog to digital converter, feedforward, 3rd order

ORIGINAL ARTICLE URL

VIEW PAPER (PDF)

* There may have been changes in the journal, article,conference, book, preprint etc. informations. Therefore, it would be appropriate to follow the information on the official page of the source. The information here is shared for informational purposes. IAD is not responsible for incorrect or missing information.