A 0.65-1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter

Authors : YALÇIN BALCIOĞLU, GÜNHAN DÜNDAR

Pages : 2410-2423

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Publication Date : 0000-00-00

Article Type : Research Paper

Abstract :This paper presents a new quantization noise suppression method for a time-to-digital converter insert ignore into journalissuearticles values(TDC); and proposes an all-digital phase-locked loop insert ignore into journalissuearticles values(ADPLL); architecture using only standard cell logic gates. Using a new multiple input multiple output insert ignore into journalissuearticles values(MIMO); quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.
Keywords : All digital phase locked loop, time to digital converter, digitally controlled oscillator, quantization noise suppression