S-visibility problem in VLSI chip design

Authors : MARZIEH ESKANDARI, MAHDIEH YEGANEH

Pages : 3960-3969

View : 12 | Download : 9

Publication Date : 0000-00-00

Article Type : Research Paper

Abstract :In this paper, a new version of very large scale integration insert ignore into journalissuearticles values(VLSI); layouts compaction problem is considered. Bar visibility graph insert ignore into journalissuearticles values(BVG); is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs insert ignore into journalissuearticles values(BsVG);. We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.
Keywords : Symbolic layout, visibility, dynamic programming, VLSI design